Electronic multipler



Jan. 31, 1961 D. M. COLLIER ETAL ELECTRONIC MULTIPLIER Original FiledJuly 29, 1955 5 Sheets-Shet 1 I BY I -1 OUTPUT a PULSE PULSE LINEARREPET'TON V sHAPER INTEGRATOR GENERATOR (82 Sec) (I VolI/SecI (10,000pps) +5 voLTAGE v COMPARATOR DELAY STOP sTART NETWORK p pm (I Sec)PROPORTIONAL REcovERY GATE CIRCUIT GENERATOR I I OUTPUT sToRAGE PuLsE RCATHODE CIRCUIT STRETCHER i g igg +E FOLLOWER (97 ;1 Sec) (4 E Sec) 5?.J- I I I PULSE I 1OO;1Sec l GENERATOR l I PuLsE :T I LINEAR INTEGRATOR lSIarr Srop I Pip Pip I: voLTAGE I I I I coMPARAToR I I fIg. E- IPRGPORTIGNAL I I GATE l I KZE PRODUCT I uni}- INTEGRATOR I I K I K K EEINVENTOR. PULSE STRETCHER Dana M. Coll/er Leighfon A. Meeks 8 James P.Palmer ATTORNEY Jan. 31, 1961 D. M. COLLIER ETAL 2,959,915

ELECTRONIC MULTIPLIER Original Filed July 29, 1955 3 Sheets-Sheet 2mobwzmw WEB 459E965 oh I m H a ||...l.|||||| l||llM|||l M M nm w a My Tv m M m n j u m w P a e v 2 H m M. m E n m a w M .W. V0 L mm v. T B AvEo E2 mm :REG 558? 9 [1 P536 MBEOZ 0F I L mm Jan. 31, 1961 D. M.COLLIER ET AL 2,96 15 ELECTRONIC MULTIPLIER Original Filed July 29, 19553 Sheets-Sheet 3 ATTORNEY United States Patent ELECTRONIC MULTIPLIERDana M-.- Collier and Leighton A. Meeks, Oak Ridge,

Tenn, and James. P. Palmer, Stony Brook, N.Y., assignors to the UnitedStates of America as represented by the United States Atomic EnergyCommission Original application July 29, 1-955, Ser. No; 525,412 nowPatent No. 2,936,119, dated May-1'0, 1960. Divided and this applicationJan. 22, 1957, Ser. No. 635,556

2 Claims. (Cl. 235-494) This invention relates to an. improvedelectronic multiplier especially adapted for use in. analog computerssuch as that described in our co-pending application S'.N. 525,412,filed July 29, 1955, now Patent No. 2,936,- 119, issued May 10, 1960.This application isa divisional application of that co-pendingapplication.

A. primary object of this, invention is to provide. a more accurate,fast multiplier circuit. Another object of this invention is to providea reliable, fast and accurate electronic multiplier for producing afinal peak voltage proportional to the product of. two time-variableinput voltages.

Yet another object of the invention. is to provide a novel electronicfast multiplier circuit, especially suited for electronic analogcomputers;

These and other objects of our invention will become apparent from thefollowing detailed description of a preferred embodiment thereof, whenread in conjunction with the appended drawings, in which:

Figure 1 is a block diagram of a novel multiplier incorporated in thesimulator.

Figure 2 is a timing chart showing the waveforms at various points inthe block diagram of Figure 1.

Figure 3 is a partial schematic diagram of a preferred form of themultiplier shown in Figure 1, and

Figure 4 shows the remainder of the multiplier circuit illustrated inblock form in Figure 1.

Multiplication isaccomplished by means of a novel system operating toproduce a rectangular pulse, the time duration of which is proportionalto one variable, using this. pulse to switch an integrator which made tointegate at a rate proportional to the other variable, and detecting;the peak voltage attained, which is then proportional to the product ofthe rate and the time inputs.

Referring now to Figure 1., the pulse repetition generator may be afrequency-stabilized blocking oscillatoropcrating. at kilocycles.Utilizing a high sampling rate minimizes the chance for error, althoughthe rate itself is not. critical. Output pulses are shaped in the pulseshaper network, which may be a one-shot multivibrator which producesrectangular pulses of about 82 microseconds duration. These pulses arefed to a linear integrator to switch it on and oif. The integrator maybe a sweep circuit having an output voltage rising at a constant rate,say 1 volt per microsecond. To avoid nonlinearity in the first fewmicroseconds or integration, the integrators are biased so that theoutput voltages start at about :3 volts and then sweeps positive andnegative,

as will be described later.

The saw-tooth wave output of the integrator is fed intothe voltagecomparator, which is also connected to ground and to a constant voltageE When the sweep 2,969,915 Patented Jan. 31, 1361 Stop Pip pulsesare-coupled through diode, clamps to the proportional gate generator,which maybe a condenser coupled toa cathode follower to set its gridvoltage. The Start Pip causes the voltage across the condenser to risequickly tov a positive value, while, the leading edge of the Stop Pipcauses the condenser to discharge quickly to a negative voltage. Thusthe output cathode follower in the gate generator produces apositive'pulse whose time duration is proportional to. the" voltage E,.The pulse from the. gate generator is coupled through diode clamps tothe grid of the product integrator to allow it to. integrate only forthe gate pulse duration, which is the period of timev between the twopips. The second variable, E, is applied as the. voltage which sets therate. of integrationof' the" product integrator, so that integrationproceeds: at-ia rate proportional to. E' for a time proportional to E.

The: output voltage of the product integrator is connected' throughdiode, clamps to a condenser in the pulse stretcher; The diodes are soarranged that the condenser voltage follows the output voltage of theintegrator up, but when the integrator voltage drops down, the diodeclamp circuit isolates the condenser to sustain it at its crest voltagemomentarily. The Stop Pip is. applied to a delay network and also to anelectronic switch coupled to a small; condenser in the storage circuit.Receipt of the pip by the switch allows. the condenser to charge for the3 microseconds duration of the Stop Pip, then the condenser'is isolatedfrom the pulse stretcher] The Stop Pip also is passed'througlr a delaynetwork, and the trailing' edge of the resulting pulse actuates aflip-flop in, the recovery: circuit to change its state toproduce,anegative signal. This signal is clamped to the. pulse stretcher c.011-denser and causes it to become uncharged. Meanwhile, the storagecircuit, now isolated. by action of the electronic switch from thechanges in voltage in the pulse stretcher, causes the output cathodefollower to-maintain a steady voltage proportional to the peak voltage.attained' by the product integrator during itslast integration. The nextpulse received from the pulse, repetition. generator restores theflip-flop in the recovery circuit to its normal. state, producing apositive signal which isv coupled to. the: pulse-stretcher circuit tocondition. it to. fol} low the product integrator during the nextintegration cycle, and at the same time this next pulse starts. the.chain of operation through the pulse shaper, linear integrator, and soforth.

Referring now to Figures 3 and 4,,tube VIA. is utilized as afree-running blocking oscillator, stabilized. at a. fret quency ofsubstantially 10, kilocycles by a tank circuitin the cathode circuit.Positive pulses are taken from the oscillator on lead and applied to.the control grid of tube VZA, each pulse causing that tube. to conduct.During conduction, its plate potentialdrops, impressing a nega: tivepulse on the control grid of tube VlB, a cathode fol.- lower.v Thecorresponding negative pulse at the cathode of tube V1B is coupledthrough condensers to. the. com trol grid of tube V213; the cathode-of.which is coupled to the cathode of tube VZA. The resultingnegative pulseat the; cathode of. tube VZB. pulls. down the cathode voltage of' tubeV2A to insure that tube V2'A conducts sufficient current to cut off tubeVl'B; The duration ot'the negative pulse'produced on lead 73 isdetermined by the values'of condensers 1.20 and resistor 121', since thecondenser charges through the resistor until tube V23 begins to'conduct,raising itscathode-potential and pulling up on. the cathode potentialof" tube VZA to cut off that tube, since, in addition, the positivepulse has ended on its grid. The potential at the grid of tube VIB thenrisestoward +300 volts, tube V'lB begins toconduct, and its cathodepotential rises to effect the end of the negative pulse on lead 73. 5

3 The lett section of tube V3 is used as an electronic switch forthelinear integrator, which may comprise an amplifier V4-V5 provided withfeed-back condensers 122 which are coupled to the B+ voltage throughlead 74 and resistor 123. To produce opposite polarity signals, bothpositive and negative, a positive-signal at the grid of V4 produces anegative pulse at its plate and at the corresponding left grid of V5. Anegative pulse appears at the left cathode of V5, and therefrom to theright grid of V4, causing a positive pulse to appear at the grid andcathode of V5. The integrator outputs are positive and negativegoingsaw-tooth voltages taken from the respective cathodes of tube V5 onleads 79, 80. When the negative pulse turns oif V3, the potential onlead 74 begins a linear rise toward +300 volts at a slope determined bythe time constant of resistor 123 and condensers 122. At the beginningof this rise, the waveforms on leads 79, 80 are not exactly linear, butare curved. To throw away this part of the non-linear portion of thewaveforms, biasing diodes 75-78 are provided to adjust the respectivegrid bias as of the secions of tube V5. The exact voltage or bias may beadjusted by the potentiometers coupled to diodes 76, 78, one grid beingbiased to about +2 volts while the other grid is biased to about 2 voltsso that the entire waveform on lead 74 is not reproduced on leads 79,80, but rather only the linear portion appears.

The signal on leads 79, 80 are respectively a positive and anegative-going saw-tooth voltage having a linear slope of apredetermined value. The positive saw-tooth is applied to the cathodesof diodes V6A, V6B, while the negative saw-tooth is applied to theplates of the diodes. The plate and cathode of diode V6A are returnedthrough resistors to ground, while the plate and cathode of tube V6B arereturned through resistors to the first variable inputs, to receivevoltages equal to +E and --E,, respectively. Normally both diodesconuduct but when they receive the two saw-tooth voltages, they are cutoff and present high impedances to the following pulse generators thetime when the cathodes begin to go more positive than the plates. Sincetube V6A is returned to ground, its cut off occurs when the saw-toothvoltages cross the ground potential line, while for tube V6B, returnedto $13,, the cut off does not occur until later, when the sawtoothvoltages overcorne the bias voltages +E and E,. The outputs across thediodes are coupled on leads 81, 82 and 87, 88 to the Start Pip throughStop Pip pulse generators, respectively. Thus diode V6B cuts off aftertube V6A by a time proportional to E,, since the saw-tooth voltages varylinearly with time.

The signals on leads 81, 82 are coupled to tubes V7, V8 where they areamplified and fed to the primary windings of transformer 83. Thesecondary windings are coupled to the control grid of one section oftube V9, which is a blocking oscillator which generates positive andnegative Start Pips on leads 85, 86. In like manner the signals on leads87, 88 are coupled to amplifier tubes V11, V12 and to transformer 89,through which the signals trigger blocking oscillator V to producepositive and negative Stop Pips on output leads 91, 92. Additionaloutput signals are taken from the secondary windings of the blockingoscilaltor transformer 90 to the storage circuit through leads 96. Itwill be noted in the above voltage comparator circuit that two diodesare used with two signals driving each diode. The use of double signalsprovide a much sharper cut off point, while by use of dual diodes in thesame envelope the drift of one diode is counter balanced by that of theother, since both diodes tend to drift in the same direction by similaramounts so that the difference in drift is very small. Moreover, byusing dual circuitry, the loss of time in firing the blocking oscillatorV9 from the amplifier tubes is not critical, since equal time delaysresult.

. Referring now to Figure 4, the proportional gate generator maycomprise diodes V21, V22 which receive the positive and negative StartPip signals on leads 85, 86.

The two diodes comprising V21 are connected in series and a condenser iscoupled between their junction and ground. Similarly the two halves ofdiode V22 are connected in series with condenser 126 coupled betweentheir junction and ground. Operation of V21 and V22 diode gates issimilar, one being for positive pulses and the other for negativepulses, so that only one will be described. When a positive Start Pip isreceived on lead 86, diodes V22 conduct and charge condenser 126. At theend of the Start Pip, the diodes no longer conduct but the condenserremains charged. Then upon occurrence of a negative Stop Pip on lead 91,the left half of diode V22 conducts away the charge on the condenser.During the time the condenser is charging, the right section of tube V23conducts, producing an output signal on lead 102 which follows thecharge on the condenser. Since the time the condenser remains chargeddepends upon the time between the Start and Stop Pips, which in turn isproportional to E the signal on lead 102 is a rectangular positive pulseof width proportional to E,.. In like fashion, lead 101 receives arectangular negative pulse of equal width.

The product integrator is an integrating amplifier simi' lar inoperation to the linear integrator, and is controlled through diodegates V24, V25 by the signals on leads 101, 102. One end of diode gateV24 is returned to the second variable input to receive a voltage equalto +E, while one end of diode gate V25 is returned to the E input toestablish the voltages toward which integration progresses during theenabled period. The input of one side of the amplifier is connectedthrough lead 127 to the control grid of tube V27A. A signal from thecathode of tube V27A is coupled to the control grid of tube V29, whichtube is cathode-coupled to tube V30. Similarly the input to the otherside of the amplifier is coupled along lead 104 to the input of tubeV27B, a signal is taken from its cathode to tube V30, and from the plateof V30 a sig nal is coupled to the grid of tube V288, the cathode ofwhich is in turn coupled through lead 106 to the grid of cathodefollower V31A. In like manner from the plate of tube V29, a signal iscoupled to the grid of tube V28A and from the cathode of that tube tothe grid of cathode follower V31B along lead 128. The cathodes of tubesV28A and V28B are coupled.

Upon receipt of the positive and negative pulses on leads 102, 101,which are coupled to the opposite ends of the diode gate V24, V25, thediodes are cut off, removing the input voltage from the input leads 127,104 to the amplifiers, and allowing the inputs to integrate toward :E.Since the duration of cut off of the diode gates is determined by thewidth of the pulses on leads 101, 102, the amplifier will integrate fora time proportional to the width and therefore to E,. Since thepotentials toward which the inputs 127, 104 proceed when cut off are +13and E, the slope of the resulting input waveform will be proportional to+E and ---B respectively. Condensers 111, 112 are connected to theoutputs of the cathode fol lowers V31A, V31B, and will charge to thecrest voltage attained by the respective followers. Diodes 109, 110allow the condensers to charge, but prevent leakage of the charge whenthe cathode voltages on the followers fall.

The Stop Pip signals on the leads 96 are coupled to diode bridges V19,V20, and V17, V18 through RC networks 97-100. The Stop Pip signals turnon the diode bridges to allow condensers 129, to charge up fromcondensers 111, 112 through leads 114, 113. These condensers are muchsmaller than condensers 111, 112 and charge up quickly without drawingsignificant charge off condensers 111, 112. The voltage acrosscondensers 129, 130, is applied to the control grids of cathodefollowers V32, and output voltages proportional to the and products arederived on leads 131, 132. When the Stop Pips end on leads 96, the diodegates V19, V20 and V17, V18 again isolate condensers 129, 130 fromcondensers 111, 112.

As may be seen from Figure 3, the Stop Pip is also applied through adelay line 93, which may be a one microsecond line, to a blockingoscillator V13, the output of which is applied through lead 95 to therecovery circuit, Figure 4. The pulse on lead 95 is applied to triggerbistable flip-flop circuit V14 to open a diode gate. The flip-flop iscoupled through cathode followers V15 to one end of the diode gate V16.When the gate is open, the diodes conduct away the charge on condensers111, 112. The next pulse from the pulse repetition generator, lead 70,is applied to tube V14 to reset the flip-flop to the normal state,closing the diode gate V16, and isolating the storage condensers 111,112.

With a sampling rate of kilocycles, it may be seen that condensers 129,130 are adjusted to receive a voltage proportional to the product of Eand E each 100 microseconds.

It will be apparent to those skilled in the art that we have provided animproved fast multiplier circuit for providing and storing temporarily acrest or peak voltage proportional to the product of two inputtime-variable voltages.

Having described our invention, We claim as novel:

1. A multiplier circuit for providing an output voltage proportional tothe product of first and second variables comprising: means forgenerating a first train of pulses of uniform duration, means forcontrolling said duration in accordance with the magnitude of said firstvariable, an integrator coupled to said generating means to receive saidpulses and adapted to deliver an electrical output, means coupled tosaid integrator for regulating the time and rate of integrationresponsive to the magnitude of said first and second variablesrespectively, means sustaining the crest voltage generated by saidintegrator, charge storage means alternately coupled to or isolated fromsaid sustaining means, and circuit means responsive to said generatingmeans for isolating said storage means from said sustaining means aftera selected time interval and for releasing said crest voltage from saidsustaining means, said storage means thereby providing an output voltageproportional to the peak integrated voltage and to the product of saidvariables.

2. A multiplier circuit comprising means for generating a train ofimpulses of selected duration, a first integrator circuit for generatinga timing voltage changing uniformly with time, means for energizing saidcircuit responsive to each of said impulses; means for generating firstand second gate signals as said timing voltage reaches selected firstand second magnitudes, a second integrator for generating a productvoltage changing uniformly with time, means for energizing said secondintegrator responsive to said first gate signal and for deenergizingsaid second integrator responsive to said second gate signal, means forstoring the crest voltage of said product voltage, means for deriving anoutput signal proportional to said crest voltage, means for deriving astop gate signal from said second gate signal, a bistable circuit havinglow and high input impedance states and coupled to said storing means tohold or empty the same, means for delaying said stop gate signal coupledto said bistable circuit to actuate said bistable circuit to the stateto empty said storing means, and means for resetting said bistablecircuit to the state for holding said storing means responsive to eachof said impulses in said train.

References Cited in the file of this patent UNITED STATES PATENTS BaumDec. 11, 1956 Johnson Apr. 7, 1959 Proceedings of the IRE (Broomall etal.), May 1952; pages 568-572.

RCA Review (Goldberg), September 1952; pp. 265- 273.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No'2,969.915 January 31, 1961 Dana M. Collier et al.2

It is hereby certified that error appears in the above numbered patentrequiring correction and that the said Letters Patent] should read as"corrected below.

Column 1, line 46, after "which" insert is lines 46 and 47, for"integate" read integrate column 2, line 52, after "lead" insert 71column 3, line 21, for "secions" read sections line 36; for "conuduct"read conduct line 45, for 'ion" read through line 16, for "through" readand line 61, for "oscilaltor" read oscillator Signed and sealed this17th day of Octoloer 1961.,

(SEAL) Attest:

ERNEST W. SW'IDER I DAVID L. LADD Attesting Officer I Commissioner ofPatents USCOMM-DC-

